As a method of testing a semiconductor memory, there is generally provided a method of generating test pattern data by a test device called a memory tester, inputting the test data to a memory to thereby perform its writing, next reading the written data from the memory, comparing the data with an expected value, and thereby determining the memory as defective when they do not coincide with each other.
In a volatile semiconductor memory such as a DRAM (Dynamic Random Access Memory), an SRAM (Static RAM) or the like, a so-called repair technology based on a redundant circuit system has been established in which a spare memory column or memory row is provided and when a fail bit is detected, its corresponding substitution is performed. In an electrically programmable and erasable nonvolatile semiconductor memory typified by a flash memory, contrary to the above, there is known a technology for configuring a system in such a manner that a failure address is detected by testing, and the detected non-failure/failure information is stored in a memory array and provided for a user, and the user avoids a fail bit through the use of the non-failure/failure information and makes use of a normal bit alone.
Further, in the volatile semiconductor memory such as the DRAM, SRAM or the like, there has been proposed the invention related to a semiconductor memory wherein a test circuit called an ALPG (Algorithmic Memory Pattern Generator) for generating test patterns (addresses and data) of a memory circuit in accordance with a predetermined algorithm and performing its test is mounted on a semiconductor chip equipped with the memory circuit (International Publication WO98/47152).
Such a test technology of ALPG system can be also applied to a nonvolatile semiconductor memory. Since, however, the flash memory or the like needs a mechanism for detecting the failure address by testing and storing the detected non-failure/failure information in the memory array as described above, it has been considered that the flash memory or the like encounters difficulties in providing the test circuit on the chip and performing its testing.
On the other hand, a test placed under a high temperature called a burn-in test or an aging test for detecting potential defective units in addition to a tester-based inspection at a wafer stage has been also performed upon testing of the semiconductor memories including the nonvolatile memory such as the flash memory or the like as well as the DRAM and SRAM. The burn-in test is performed while mounting several tens to several hundreds of memories each placed in a state of being assembled into a package, onto a printed board called a burn-in board, collectively inserting the board into a heating chamber in the form of several tens of sheets and applying test patterns from a control device.
The nonvolatile semiconductor memory encounters difficulties in stabilizing write and erase characteristics in the case of the present process technology. Therefore, a write and erase-repeated write/erase cycle test unexecuted upon testing of the volatile semiconductor memory such as the DRAM (Dynamic Random Access Memory), the SRAM (Static RAM) or the like, has been performed within a burn-in apparatus.
FIG. 10 shows a procedure for testing a conventional nonvolatile semiconductor memory after the assembly thereof into a package. As shown in the same drawing, memories subsequent to the completion of an assembly step of Step S1 are shifted to a burn-in step (Step S2), where they are respectively mounted onto a burn-in board and subjected to a burn-in test in normally several hundreds of units over 10 hours or so. Further, a write and erase-repeated write/erase cycle test is performed within the burn-in apparatus (Step S3). Afterwards, the procedure proceeds to a sorting or selection step (Step S4) using a memory tester, where a DC test, an AC test and a function test, etc. are performed, whereby only ones judged as non-defective are shipped.
However, the conventional test method is accompanied by a problem that since the tests using the memory tester can be performed only in a few or several tens of units, they are inefficient as compared with the burn-in apparatus capable of performing tests in several thousands of units, and since an expensive tester capable of performing the function test is required in the selection step in Step S4, the rate of a test cost taken up in a product unit price becomes so high.
Described specifically, the cost of the tester capable of performing the function test takes several tens of times as much in cost as the most expensive device with a test function, of a tester and a burn-in apparatus capable of performing a DC test and an AC test alone. Since the conventional test method makes use of such an expensive tester and can be executed only in the few or several tens of units, the number of testers is limited even if the efficiency of a manufacturing process is made high. Therefore, the time required to perform each test by the tester was brought into a bottleneck, so that production efficiency was remarkably reduced. Since the number of expensive testers must be increased to increase the number of memories testable per unit time, a problem arises in that a huge or tremendous capital investment is required.
An object of the present invention is to provide a test technology capable of testing a nonvolatile semiconductor memory without using such an expensive tester as to be capable of performing a function test.
Another object of the present invention is to provide a test technology capable of increasing the number of nonvolatile semiconductor memories capable of simultaneously performing a function test.
A further object of the present invention is to provide a test technology capable of causing a nonvolatile semiconductor memory to perform its self-test without increasing a chip size so much.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.